(1) Field of the Invention
The present invention generally relates to a synchronous semiconductor device, such as a synchronous dynamic random access memory (SDRAM), and more particularly to a synchronous semiconductor device in which operations may be performed in a power down mode (a PD mode) and in a clock suspending mode (a CSUS mode). In the PD mode, DC current which should be supplied to input circuits is cut off to reduce power dissipation. In the CSUS mode, an internal clock signal which is used as a synchronous signal is suspended so that chip-access from an external unit is suspended.
(2) Description of the Related Art
A SDRAM (Synchronous Dynamic Random Access Memory) which operates in synchronism with a clock signal supplied from an external unit is generally formed as shown in FIG. 1.
Referring to FIG. 1, an SDRAM has a timing control circuit 100, a memory control circuit 200 and a memory bank 300. The timing control circuit 100 is provided with pads P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.4, . . . to which a RAS (Row Address Strobe) signal, a CAS (Column Address Strobe) signal, a WE (Write Enable) signal, a CKE (Clock Enable) signal, a CLK (an external Clock) signal and other external signals are input. In the memory bank 300, memory cells (cell transistors) are arranged. The timing control circuit 100 controls, based on the CLK signal input to the pad P.sub.5, timing at which the external signals are input to the other pads. The external signals which are controlled by the timing control circuit 100 are supplied to the memory control circuit 200. The memory control circuit 200 supplies to the memory bank 300 operation signals (commands), such as a read-operation signal, a write-operation signal, a refresh-operation signal and a precharge-operation signal each of which are represented by combination of the external signals supplied from the timing control circuit 100. In accordance with the operation signals, operations, such as a read-write operation, are executed in the memory bank 300.
In the SDRAM, the operations may be executed in a power down mode (a PD mode) and in a clock suspending mode (a CSUS mode). In the PD mode, the DC currents which are to be supplied to input circuits for performing input operations of external signals are cut off when there is no chip-access, so that the power dissipation can be reduced. In the CSUS mode, the internal clock signal synchronized with the external clock signal is suspended to prohibit the chip-access.
The SDRAM in which the memory bank 300 is inactive is set in the PD mode when it is detected, in synchronism with the external clock signal, that the CKE (Clock Enable) signal has a low level as shown in FIG. 2. The PD mode is not maintained for a time equal to or longer than the refresh time t.sub.REF. The SDRAM in which the memory bank 300 is active is set in the CSUS mode when it is detected, in synchronism with the external clock signal, that the CKE signal has a low level as shown in FIG. 3. When the SDRAM is set in the CSUS mode, the internal clock signal, synchronized with the external clock signal, is suspended. In an example shown in FIG. 3, the internal clock signal is suspended after one clock from when it is detected that the CKE is at the low level. That is, an CKE latency is one clock. As the result of suspending of the internal clock signal, in the case of a read-operation, read data is not varied while the internal clock signal is suspended (see data Q2 and Q3 in FIG. 3). In the case of a write-operation performed in synchronism with the internal clock signal, data is not written while the internal clock signal is suspended.
In both the cases of entry of the PD mode and the CSUS mode, the CKE signal has to fall to the low level. In a state where the CKE signal has the low level, in accordance with the internal state (the memory bank 300 is in the active state or in the inactive state) of the SDRAM, either the PD mode or the CSUS mode is selected.
The timing control circuit 100 in the conventional SDRAM generates an internal RAS signal (hereinafter referred to as a rasz signal). The rasz signal rises when the memory bank 300 is made active and falls when the memory bank 300 is made inactive. The rasz signal is used to reset the word line (WL). When the rasz signal has the low level and the CKE signal supplied from the external unit falls to the low level, the timing control circuit 100 outputs a PD control signal so that the SDRAM is set in the PD mode. The PD control signal is used to cut off the DC currents which are to be supplied to the respective input circuits. On the other hand, when the rasz signal has a high level and the CKE signal falls to the low level, the timing control signal 100 outputs a CSUS control signal so that the SDRAM is set in the CSUS mode. The CSUS control signal is used to suspend the internal clock signal.
The SDRAM is permitted an auto-precharge command operation. In accordance with a state of a predetermined address bit at the time of input of an operation command regarding a CAS (Column Address Strobe), the auto-precharge command operation can be executed. After the operation regarding the CAS is completed, a precharge operation is automatically executed in an operation regarding a RAS (Row Address Strobe). In the precharge operation, the potential of the word line is made to fall so that cell transistors in the memory bank 300 are cut off. For example, when a read command (READA) with the auto-precharge command is activated, the precharge operation is executed with reading of data (DQ) after the read command is detected in synchronism with the clock signal, as shown in FIG. 4. During a period (t.sub.RP) is which the precharge operation is executed, a new command can not be issued. In addition, for example, when a write command (WRITA) with the auto-precharge command is activated, the write operation for data and the precharge operation are executed after the write command is detected in synchronism with the clock signal, as shown in FIG. 5. The precharge operation starts after a write recovery time t.sub.RWL elapses from the end of the burst. During the period t.sub.RP in which the precharge operation is executed, the new command can not be issued. In the read operation and the write operation as shown in FIGS. 4 and 5, the CAS latency which represents delay of the operation is set at two clocks (CL=2), and the burst length corresponding to the data length is set at two clocks (BL=2).
To indicate a state where the precharge operation described above is executed, the rasz signal which has risen in synchronism with the CLK signal is made to fall. That is, the level of the rasz signal indicates whether the precharge operation is executed.
In the conventional SDRAM in which the PD mode and the CSUS mode are distinguished from each other using the rasz signal which indicates whether the auto-precharge operation is executed, the following inconvenience occurs.
As shown in FIG. 6, in a state where the memory bank 300 is in the active state so that the data (DQ) is output in synchronism with the internal clock signal CLK, the rasz signal has a high level. In this state, when the CKE falls to a low level, the SDRAM is set in the CSUS mode. In addition, when it is detected, in synchronism with the internal clock signal CLK, that the burst is completed (at a time (a)), the precharge operation starts and the rasz signal falls to the low level. The data then falls to the low level or rises to the high level. At this time, if the CKE has the high level, the SDRAM is set in the PD mode, so that the power to the input circuit for the external clock signal is turned off. As a result, immediately after the rasz signal falls, the internal clock signal is suspended so that an output transistor which should be operated with synchronism with the internal clock is maintained in a current state. At this time, if the output transistor has not yet been in a high-impedance state (a state where data is not output) after the data is completely output, the SDRAM in which the output transistor is in a conductive state (a state where the data is output) is maintained in the PD mode.
In the case shown in FIG. 6, the CAS latency is set at one clock (CL=1) and the burst length is set at four clocks (BL=4).
FIG. 7 shows a case where the CAS latency is set at two clocks (CL=2) and the burst length is set at four clocks (BL=4). FIG. 8 shows a case where the CAS latency is set at three clocks (CL=3) and the burst length is set at four clocks (BL=4). In the cases shown in FIGS. 7 and 8, after one clock from the end of the bust signal, the precharge operation starts. In these cases, after and before the rasz signal falls, the inconvenience, based on the block at the time (a), occurs in the same manner as in the above case.
Thus, the conventional SDRAM has to be used with the limit in which the CKE is inhibited from falling before and after the rasz signal falls.